One or more embodiments of the present invention pertain to methods for use in fabricating gates and capacitors in integrated circuit (xe2x80x9cICxe2x80x9d) devices.
As pointed out in an article by H. Shimada et al. entitled xe2x80x9cTantalum Nitride Metal Gate FD-SOI CMOS FETs Using Low Resistivity Self-Grown bcc-Tantalum Layerxe2x80x9d in IEEE Transactions on Electron Devices, Vol. 48, No. 8, pp. 1619-1626, August 2001 (the xe2x80x9cShimada articlexe2x80x9d), as complementary metal oxide semiconductor (CMOS) devices are scaled down aggressively to improve their performance, advanced gate technology has become a concern. For a polysilicon gate CMOS process, it is difficult to prevent a gate dopant (for example, boron) from penetrating through a thin gate oxide in ULSI technology. This results in instability in Vth (voltage threshold), a degradation of gate oxide reliability, and a degradation of current drivability due to polysilicon gate depletion. Further, the sheet resistance of a gate electrode using silicide technology is high in scaled devices, and is not large enough to maintain a proper aspect ratio for a gate stack. Still further, scaled polysilicon gate devices require considerably higher channel doping to achieve acceptable Vth values, resulting in lower channel mobility due to impurity scattering. In view of these limitations, the use of a refractory metal electrode is an attractive alternative. The article further discloses tantalum nitride (TaNx) gate devices having a conventional planar gate structure to achieve low gate sheet resistance and low specific contact resistance.
FIG. 1 shows a block diagram of a cross section of a wafer or substrate having devices being fabricated thereon (a work-in-progress), which work-in-progress includes a TaNx/Ta/TaNx stacked metal gate structure. As shown in FIG. 1, structure 1000 includes: (a) wafer or substrate 1010 (for example, silicon wafer or substrate 1000); (b) gate oxide layer 1020 disposed or formed over wafer or substrate 1010; (c) metal gate stack 1030 that includes TaNx layer 1040 disposed or formed over gate oxide layer 1020, Ta layer 1050 disposed or formed over TaNx layer 1040, and TaNx layer 1060 disposed or formed over Ta layer 1050; and (d) patterned photoresist layer 1070 disposed or formed over TaNx layer 1060. TaNx layer 1060 is a protective capping layer used to protect metal gate stack 1030 from an oxidizing ambient such as might be present during source/drain annealing or ILD deposition. In addition, a TaNx layer is well known as serving as a barrier for copper diffusion. For one example, gate oxide layer 1020 has a thickness of about 3.8 nm; TaN layer 1040 has a thickness of about 40 nm; Ta layer 1050 has a thickness of about 120 nm; and TaNx layer 1060 has a thicknesses of about 40 nm.
Using the above-disclosed metal gate stack on a thin gate oxide to form an FET requires a selectivity of TaN/oxide of about 100 to 1. However, achieving such a high selectivity typically results in undercutting at an interface between the TaN layer and the gate oxide unless a passivation layer is also available at the metal gate stack sidewalls. The Shimada article discloses etching such a metal gate stack using an SF6/SiCl4 chemistry, however, such an etch chemistry does not provide suitable TaN/oxide selectivity, and will also produce undercutting.
One or more embodiments of the present invention advantageously solve one or more of the above-identified problems in the art. Specifically, one embodiment of the present invention is a method used to fabricate devices on a substrate, which method is utilized at a stage of processing wherein a metal gate stack is disposed or formed over a gate oxide, which metal stack includes a refractory metal layer disposed or formed over a refractory metal barrier/adhesion layer, which method comprises steps of: (a) etching the refractory metal layer and stopping on or in the refractory metal barrier/adhesion layer; and (b) etching the refractory metal barrier/adhesion layer using a passivation etching chemistry without oxygen.